The host connector is backward compatible with the standard 3. It was concluded that doubling the native SATA speed would take too much time, too many changes would be required to the SATA standard, and would result in a much greater power consumption when compared to the existing PCI Express bus. Having a smaller and more flexible physical specification, together with more advanced features, the M.
Supported host controller interfaces and internally provided ports are a superset to those defined by the SATA Express interface. Essentially, the M. Like M. In order to provide maximum backward compatibility the U. The physical layer defines SATA's electrical and physical characteristics such as cable dimensions and parasitics, driver voltage level and receiver operating range , as well as the physical coding subsystem bit-level encoding, device detection on the wire, and link initialization.
Physical transmission uses differential signaling. When the SATA-link is not in use example: no device attached , the transmitter allows the transmit pins to float to their common-mode voltage level. When the SATA-link is either active or in the link-initialization phase, the transmitter drives the transmit pins at the specified differential voltage 1.
This scheme serves multiple functions required to sustain a differential serial link. The sequence also maintains a neutral DC-balanced bitstream, which lets transmit drivers and receiver inputs be AC-coupled. Generally, the actual SATA signalling is half-duplex , meaning that it can only read or write data at any one time. In particular, the PHY layer uses the comma K A specific four-symbol sequence, the ALIGN primitive, is used for clock rate-matching between the two devices on the link.
Other special symbols communicate flow control information produced and consumed in the higher layers link and transport. Separate point-to-point AC-coupled low-voltage differential signaling LVDS links are used for physical transmission between host and drive. During the link-initialization process, the PHY is responsible for locally generating special out-of-band signals by switching the transmitter between electrical-idle and specific 10b-characters in a defined pattern, negotiating a mutually supported signalling rate 1.
During this time, no data is sent from the link-layer. FISs are packets containing control information or payload data. Each packet contains a header identifying its type , and payload whose contents are dependent on the type. The link layer also manages flow control over the link. Layer number three in the serial ATA specification is the transport layer. The transport layer handles the assembly and disassembly of FIS structures, which includes, for example, extracting content from register FISs into the task-file and informing the command layer.
In an abstract fashion, the transport layer is responsible for creating and encoding FIS structures requested by the command layer, and removing those structures when the frames are received. When DMA data is to be transmitted and is received from the higher command layer, the transport layer appends the FIS control header to the payload, and informs the link layer to prepare for transmission. The same procedure is performed when data is received, but in reverse order.
The link layer signals to the transport layer that there is incoming data available. Once the data is processed by the link layer, the transport layer inspects the FIS header and removes it before forwarding the data to the command layer. SATA uses a point-to-point architecture. The physical connection between a controller and a storage device is not shared among other controllers and storage devices.
The multiplier performs the function of a hub; the controller and each storage device is connected to the hub. This Legacy Mode eases OS installation by not requiring that a specific driver be loaded during setup, but sacrifices support for some vendor specific features of SATA. Often, which ports are disabled is configurable. Examples of such provisions include:. This can cause data corruption in operating systems that do not specifically test for this condition and limit the disk transfer speed.
SATA 1. Most devices that are only SATA 1. SCSI buses also allow connection of several drives on one shared channel, whereas SATA allows one drive per channel, unless using a port multiplier. As those two worlds overlapped, the subject of reliability became somewhat controversial.
Note that, in general, the failure rate of a disk drive is related to the quality of its heads, platters and supporting manufacturing processes, not to its interface. Many server and RAID systems provide hardware support for transparent hot swapping. From Wikipedia, the free encyclopedia. Computer bus interface for storage devices.
For other uses, see SATA disambiguation. This article has multiple issues. Please help improve it or discuss these issues on the talk page. Learn how and when to remove these template messages. This article's use of external links may not follow Wikipedia's policies or guidelines. Please improve this article by removing excessive or inappropriate external links, and converting useful links where appropriate into footnote references.
February Learn how and when to remove this template message. This article's lead section may be too short to adequately summarize the key points. Please consider expanding the lead to provide an accessible overview of all important aspects of the article. January A seven-pin SATA data cable left-angled version of the connector. SATA 3. Not to be confused with SATAe.
Main article: eSATAp. Main article: M. This section does not cite any sources. Please help improve this section by adding citations to reliable sources. Unsourced material may be challenged and removed. January Learn how and when to remove this template message. See also: Port multiplier. This section needs expansion. You can help by adding to it.
October July See also: List of device bit rates. Electronics portal. Archived from the original on Retrieved January 7, Archived from the original PDF on October 9, March 1, Retrieved July 8, Future plc. Retrieved 30 August Archived PDF from the original on ISBN Archived from the original PDF on Archived from the original on 25 October Retrieved 19 March Archived from the original on 2 March Retrieved April Archived from the original on 2 February Retrieved 4 December May 27, Archived PDF from the original on 11 June Retrieved 3 July What else is new in SATA specification v3.
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